Power supplied to a central processing unit (CPU) occurs through a power distribution network. The power distribution network starts with a power supply that generates an appropriate DC voltage. The power supplied to the CPU must traverse from the power supply and across the power distribution network before it reaches the CPU. The power distribution network has characteristics that may affect the operation of the CPU.
FIG. 1 shows a depiction of a conventional CPU system (10). The CPU system (10) includes a printed circuit board (PCB) (12). The PCB (12) is a central platform on which various components are mounted. The PCB (12) has multiple layers that contain traces that connect the power supply and signals to the various components mounted on the PCB (12). Two layers, a system power supply layer (14) and a system ground layer (16), are shown in FIG. 1.
The system power supply layer (14) and the system ground layer (16) provide power to a CPU (20). The power supplied to the CPU (20) must traverse from a DC source (not shown) to a package (18) on which the CPU (20) is mounted using the system power supply layer (14) and the system ground layer (16). Other components are also mounted on the PCB (12) that generally attempt to maintain a constant voltage supplied to the CPU (20). These components may include, but are not limited to, an air-core inductor (24), a power supply regulating integrated circuit (26), switching transistors (28), a tantalum capacitor (30), and electrolytic capacitors (32).
In FIG. 1, the power supplied to the CPU (20) traverses from the DC source (not shown) and across the power distribution network created by the system power supply layer (14) and the system ground layer (16). Each layer (14, 16) creates a plane within the PCB (12). A variety of different types and different locations of capacitors are used to help maintain a constant voltage supplied to the CPU (20). Electrolytic capacitors (32) mounted on the PCB (12) connect between the system power supply layer (14) and the system ground layer (16). The package (18), similar to the PCB, may include multiple planes and interconnections between the planes to provide a connective substrate in which power and signals traverse. Ceramic capacitors (22) mounted on the package (18) connect between a package power supply signal (not shown) and a package ground signal (not shown).
Due to active switching of circuit elements on the CPU (20), the power required by the CPU (20) changes. The active switching causes power supply noise. Additional components may be included to minimize the power supply noise generated by the CPU. For example, ceramic capacitors (22) near the CPU (20) act as local power supplies by storing charge.
The addition of components reduces the power supply impedance at most frequencies; however, localized impedance peaks may exist. The impedance peaks indicate a resonance in the power distribution network. The resonance is formed when parasitics in the power distribution network and components connected to the power distribution network are excited at a particular frequency.
The parasitics include the inherent inductance, resistance, and capacitance that may occur in the CPU (20) (or other chips or integrated circuits), package (18), and power distribution network. In particular, the resonance may be formed from the power distribution network and a xe2x80x9cparasitic tank circuitxe2x80x9d that includes the chip capacitance and package inductance.
FIG. 2 shows a prior art schematic of a power distribution network for a CPU. A DC power supply (202) is shown at the left. Two power supply lines (292, 294) supply power to a CPU located between the two power supply lines (292, 294). The circuit elements between the DC power supply (202) and the power supply lines (292, 294) model both the inherent parasitics of the power distribution network and added components.
In FIG. 2, the DC power supply (202) connects to the power distribution network through a power supply connector. The power supply connector has inherent parasitics modeled by resistors (204, 208) and inductors (206, 210). The electrolytic capacitors (32 in FIG. 1) are represented as bulk capacitors in FIG. 2. Capacitors do not only have a capacitive behavior but also a small resistive and inductive behavior. Thus, the inductor (212), resistor (214), and capacitor (216) model the bulk capacitors. The parasitic behavior of the PCB planes (system power supply layer (14) and system ground layer (16) in FIG. 1) is modeled as resistors (218, 222) and inductors (220, 224).
In FIG. 2, the power distribution network may include multiple power supply planes and connections to a package (or multiple packages). The inherent series parasitics of the power distribution network are modeled by resistors (232, 236, 240, 244) and inductors (234, 238, 242, 246).
Multiple planes and interconnections between the planes may create parasitics in parallel with the power supply. In FIG. 2, inherent parallel parasitics created by the power distribution network are modeled. Also, additional capacitance in parallel with the power supply may help maintain a constant voltage. The additional capacitance may be connected between the power supply planes, for example, ceramic capacitors may connect between the system power supply plane and system ground plane. The inductance (226), resistance (228), and capacitance (230) model some of the parasitics and components in parallel with the power supply (202). Additional inherent parasitics and added capacitance local to the CPU may be modeled. The ceramic capacitors (22 in FIG. 1) and other inherent parasitics created by the package multiple planes and interconnections are modeled by inductor (248), resistor (250), and capacitor (252).
A package may connect to a CPU using a grid of solder bumps. In FIG. 2, the inherent parasitics created by the solder bumps are modeled by inductors (254, 258) and resistors (256, 260). On the CPU, various forms of chip capacitance may be used to further stabilize the power supply. Low equivalent series resistance (ESR) local decoupling capacitors are modeled by resistor (262) and capacitor (264). High ESR global decoupling capacitors are modeled by resistor (266) and capacitor (268). Non-switching logic on the CPU is modeled by resistor (270) and capacitors (272, 274). Switching logic on the CPU is modeled by variable resistors (276, 278) and capacitors (280, 282).
In FIG. 2, the schematic of the power distribution network may be used to simulate the impedance observed by the CPU, as represented by xe2x80x9cZ.xe2x80x9d To simulate the impedance, a 1 Ampere AC current source (290) injects current onto power supply line (292). The measured voltage, VM, between two power supply lines (292, 294) may be used to calculate the impedance. The impedance Z is equal to VM divided by 1 Ampere. By varying the frequency of the 1 Ampere AC current source (290), a frequency versus impedance graph may be drawn. Over a particular range of frequencies, the impedance increases because the circuit formed by the chip and package resonates. The resonance from the chip and package may affect the operation of the CPU.
According to one aspect of the present invention, an apparatus for reducing a power supply impedance of an integrated circuit comprises a package on which the integrated circuit is mounted; a power supply path on the package adapted to receive power from a power supply where the power supply path comprises a first power supply line and a second power supply line to provide power to the integrated circuit; at least one digital potentiometer connected between the first power supply line and the second power supply line to reduce the power supply impedance of the integrated circuit; and a test processor unit operatively connected to the at least one digital potentiometer where the at least one digital potentiometer is responsive to the test processor unit.
According to one aspect of the present invention, a method for reducing an impedance of a power supply path of an integrated circuit where the power supply path comprises a first power supply line and a second power supply line, the method comprises selectively adjusting a value of a digital potentiometer connected between the first power supply line and the second power supply line to reduce an impedance of the power supply path; determining the impedance of the power supply path of the integrated circuit; and storing a desired value determined from the selectively adjusting in a storage device.
According to one aspect of the present invention, an apparatus for reducing an impedance of a power supply path of an integrated circuit connected to the power supply path where the power supply path comprises a first power supply line and a second power supply line, the apparatus comprises means for selectively adjusting a value of a digital potentiometer connected between the first power supply line and the second power supply line to reduce an impedance of the power supply path; means for determining the impedance of the power supply path of the integrated circuit; and means for storing a desired value determined from the selectively adjusting in a storage device.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.